The present invention relates in general to the protection of integrated circuits (IC) and, more particularly, to a voltage clamp circuit having an output for clamping the voltage applied thereto to a predetermined value. The need for protection of vulnerable areas within an IC from an undesirable voltage is well known and applicable to most if not all bipolar technologies. In standard bipolar processes for example, junction diodes are formed between adjacent P-substrate and N-epitaxial (N-epi) regions. N-epi regions are commonly coupled to the IC pins rendering the junction vulnerable to a negative voltage. Should an unknown negative voltage of sufficient magnitude be applied to the IC pin, the P-substrate/N-epi junction diode (N-epi diode) would become forward biased thereby injecting electrons into the P-substrate which could seriously degrade, or even destroy the IC.
A typical method to protect the IC is to couple the output of a voltage clamp circuit to the vulnerable N-epi regions at the particular IC pin. The voltage clamp circuit is then responsive to the output signal of an external voltage supply having a finite output impedance for limiting the voltage applied to the IC pin to a predetermined value which is less than the cutin potential of the N-epi diode. When the external voltage supply attempts to assert a negative voltage, the voltage clamp circuit then sources a current which develops a potential across the output impedance of the voltage supply thereby limiting the voltage applied to the IC pin.
A known voltage clamp circuit may be realized with an NPN transistor having an emitter coupled to the vulnerable N-epi region, and a base coupled to the anode of a diode. A voltage, typically ground potential, is applied to the cathodeof the diode. The collector and base of the NPN transistor are coupled to the input and utput of a PNP current mirror circuit respectively forming a feedback loop from the collector to the base of the NPN transistor. Ideally, the NPN transistor turns on when the magnitude of the voltage applied to its emitter passes through ground potential in the negative direction. The voltage clamp circuit then sources a current of appropriate magnitude to the external voltage supply which is coupled to the emitter of the NPN transistor to limit the applied voltage to approximately ground potential thereby protecting the N-epi region as described above.
It is not uncommon during normal operation for the magnitude of the externally applied voltage to be equal to ground potential, thus it would be undesirable to turn on the voltage clamp circuit and source current to the external voltage supply under this condition. Although the aforedescribed voltage clamp circuit can achieve a below ground clamping threshold by applying a negative voltage to the cathode of the diode, such negative power supplies are not readily available in many circumstances including automotive applications. Another problem with the known voltage clamp circuit is the inherent slow transient response of the PNP current mirror feedback loop. Should the slew rate of the external voltage supply exceed the loop response time of the PNP current mirror, the reaction of the NPN transistor would lag the external voltage supply which could allow the voltage applied to the N-epi region to exceed the cutin potential thereby forward biasing the N-epi diode and injecting electrons into the P-substrate.
Hence, there is a need for an improved voltage clamp circuit for clamping the voltage applied to a N-epi region to predetermined negative value without utilizing a negative power supply. Also, the transient loop response time of the improved voltage clamp circuit must be less than the estimated maximum slew rate of the external voltage supply.